Seagate Internship Program 2021

Seagate Internship Program 2021:-

Seagate Internship hiring candidates for the role of Intern V – VLSI Engineering for the Location Pune, India. The complete details about Seagate Internship Program 2021 as Follows

30 LPA Highest salary offered – 1650 on & off campus drives annually – 5 Lac + Jobs created in a year – Register & Apply to jobs( BE/BTech preferred )

Company Name:- Seagate

Position:– Intern V – VLSI Engineering

Stipend:- As per the company standards

Work Location :– Pune , India.

Employment Type:- Intern

Excellent Part-time Income opportunity – Earn from your comfort of home, Signup for free

Requirements:-

Knowledge of ASIC design flow and tools
Good understanding of Circuit design and Logic design
Good understanding of analog circuit design and concepts
Good understanding of timing concepts like setup time, hold time requirements, calculations of maximum frequency of circuit operations, effect of transition and load on circuit performance and power
Basic understanding of CMOS fabrication process
Basic understanding of layout design for CMOS and BJT
Basic understanding of power dissipation in different types of circuits
Self-motivated & a strong team player
Strong analytical skills
Ability to quickly learn new tools and technologie

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Responsibilities:-

Be able to work on block level Physical Design implementation using two or more EDA tools for Synthesis, floor-planning, placement, timing analysis, IR drop analysis and Physical verification
Do basic synthesis set-up, understand the inputs required to perform the tasks, understand the tasks, understand Semicustom IC design flow using IP libraries, concepts of Verilog netlist, meaning of timing constraints and QOR checks
Work on Physical design tasks including floor-planning, placement, clock tree synthesis, routing, timing analysis, IR drop analysis and equivalence checking for flat designs
Work on Physical verification tasks including creating setup and scripts for DRC, LVS, Antenna and density checks, report generation, analysis, debug and implementing the fixes in the physical design database

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Work on Timing analysis tasks including understanding of sign-off corners and modes, report generation, analysis of the reports and suggesting timing/DRC fixes to fix the violations
Work on IR drop analysis, be able to do basic set-up, understand the inputs required to perform the tasks, understand the tasks, reports generation and analysis, suggest fixes for the violations. Understand static, dynamic IR and EM analysis
Complete internship project as per plan

Your experience includes:

ASIC design flow, EDA tools for Physical design implementation
Synthesis, DFT, Place and Route, Floor Planning, Timing Analysis, IR drop Analysis
Perl, Tcl, Shell or other scripting languages